{"rewrite":{"id":"r_287d1dbec4287fa2e2c6138b","clusterId":"c_5cfb66d2083d1a81698b0439","slug":"intel-s-wildcat-lake-drops-foveros-for-mcp-to-cut-costs","model":"deepseek-v4-flash","headline":"Intel's Wildcat Lake Drops Foveros for MCP to Cut Costs","summary":"Intel detailed Wildcat Lake at Hot Chips, confirming the processor abandons the Foveros packaging used since Meteor Lake for a two-tile MCP. The CPU and GPU tile runs on Intel 18A with Cougar Cove P-cores, while the Platform Controller Tile moves to TSMC N6. The tiles connect over UCIe, Intel's first product use of the interface, held to a conservative 8Gbps to control bit error rates.","whyItMatters":"Wildcat Lake's packaging shows Intel prioritizing cost over the flexibility of Foveros, pairing a reused Intel 18A compute tile with a TSMC N6 controller tile and a deliberately cautious UCIe debut.","webCardHtml":"\u003cp\u003eIntel weighed a monolithic design for Wildcat Lake and passed on it. A single die would remove the D2D PHY, but the larger die would cut yield and push I/O buffers onto a more expensive process node, so the MCP route won on cost despite the added PHY area.\u003c/p\u003e\u003cp\u003eThe one gamble is UCIe, the interface linking the CPU and GPU tile to the Platform Controller Tile. It is Intel\u0026#39;s first product use of the standard, and the signal rate is capped at 8Gbps because faster links pushed bit error rates past acceptable limits, requiring retry and FEC logic that would add complexity and schedule risk.\u003c/p\u003e","blueskyPost":"Intel's Wildcat Lake drops Foveros for a two-tile MCP to save cost: Cougar Cove compute on Intel 18A, controller tile on TSMC N6, linked by UCIe at a conservative 8Gbps. It is Intel's first UCIe product, and the safe speed was a deliberate call.","twitterPost":"Intel's Wildcat Lake abandons Foveros for a two-tile MCP. Compute tile on Intel 18A, controller tile on TSMC N6, joined by UCIe at 8Gbps. Intel's first UCIe product, and the conservative link speed was deliberate.","threadsPost":null,"newsletterBlurb":"Intel detailed Wildcat Lake at Hot Chips, confirming the budget processor drops Foveros for a two-tile MCP. The compute tile reuses Cougar Cove on Intel 18A, the controller tile goes to TSMC N6, and the two connect over UCIe at a conservative 8Gbps, a first for Intel.","attributionJson":"[{\"source\":\"ASCII.jp\",\"url\":\"https://ascii.jp/elem/000/004/431/4431683/?rss\",\"title\":\"Hot Chipsで明かされた「Wildcat Lake」の全貌　Foverosを捨てMCPを選んだインテルの舞台裏\"}]","lintFlagsJson":null,"lintHits":0,"costUsd":0,"inputTokens":5994,"outputTokens":3008,"status":"published","repairAttempts":0,"nextRepairAt":null,"factsAttemptedAt":1788752679,"createdAt":"2026-09-07T03:42:32.000Z","publishedAt":"2026-09-07T03:43:22.000Z","updatedAt":"2026-09-07T03:43:22.000Z"},"cluster":{"id":"c_5cfb66d2083d1a81698b0439","canonicalTitle":"Hot Chipsで明かされた「Wildcat Lake」の全貌　Foverosを捨てMCPを選んだインテルの舞台裏","representativeArticleId":"a_828245aa080630c2c084de79","sourceCount":1,"writtenSourceCount":1,"writeAttempts":0,"isSolo":true,"entitiesJson":"{\"anime_titles\":[],\"manga_titles\":[],\"work_titles\":[],\"studios\":[],\"people\":[],\"type\":\"news\",\"domain\":\"other\",\"is_roundup\":false}","contentType":"news","status":"published","firstSeenAt":"2026-09-07T03:00:00.000Z","lastSeenAt":"2026-09-07T03:00:00.000Z","updatedAt":"2026-09-07T03:43:20.000Z"},"attribution":[{"source":"ASCII.jp","url":"https://ascii.jp/elem/000/004/431/4431683/?rss","title":"Hot Chipsで明かされた「Wildcat Lake」の全貌　Foverosを捨てMCPを選んだインテルの舞台裏"}],"entities":{"anime_titles":[],"manga_titles":[],"work_titles":[],"studios":[],"people":[],"type":"news","domain":"other","is_roundup":false},"keyFacts":null}