{"rewrite":{"id":"r_3b5c84600dbef65fc3828aab","clusterId":"c_dd6884db5260706dc210c384","slug":"ibm-announces-0-7nm-node-chip-with-3d-nanostack-transistors","model":"deepseek-v4-flash","headline":"IBM Announces 0.7nm Node Chip With 3D Nanostack Transistors","summary":"IBM announced on June 25, 2026, what it calls the world's first 0.7nm (7 angstrom) node chip technology, using a three-dimensional transistor architecture named \"nanostack.\" The chip integrates approximately 100 billion transistors on a fingernail-sized area, nearly doubling transistor density compared to IBM's 2nm node chip from 2021. IBM claims the technology can deliver up to 50% higher performance or 70% higher energy efficiency versus the 2nm node. The nanostack structure stacks transistors vertically using 3D sequential integration with staggered placement, allowing different material combinations per layer to optimize performance and power. IBM validated the design through ultra-thin dielectric bonding in CMOS integration and demonstrated working CMOS inverters. At the VLSI 2026 symposium, IBM showed that SRAM bit cells using nanostack can reduce height by 40%, enabling more SRAM on the same chip area for AI data bandwidth. IBM says the technology extends Moore's Law for at least 10 years, with a path to production within five years. IBM does not manufacture chips itself and has not disclosed commercialization partners, but conducts research at a facility in Albany, New York, expected to use ASML's High NA EUV lithography equipment.","whyItMatters":"The announcement marks the first time a major chip designer has publicly demonstrated a working sub-1nm node logic technology, shifting the industry debate from whether miniaturization can continue to how quickly 3D transistor stacking reaches mass production.","webCardHtml":"\u003cp\u003eIBM validated the nanostack design through ultra-thin dielectric bonding in CMOS integration and demonstrated working CMOS inverters, proving the structure is physically manufacturable and capable of actual computation. Jay Gambetta, IBM Research Director and IBM Fellow, said, \u0026#34;With the nanostack architecture, we are not just shrinking transistors; we are reinventing how chips are built, significantly boosting processing performance and energy efficiency.\u0026#34;\u003c/p\u003e\u003cp\u003eAt the VLSI 2026 symposium, IBM showed that SRAM bit cells using nanostack can reduce height by 40%. SRAM is a memory for high-speed read/write operations that supports high-bandwidth data transmission required for AI processing. Reducing the footprint of SRAM bit cells allows more SRAM on the same chip area, facilitating high-bandwidth data access for AI workloads.\u003c/p\u003e\u003cp\u003eIBM does not manufacture chips for mass production itself and has not disclosed partner companies for commercializing the technology. IBM and its partners conduct research at a semiconductor facility in Albany, New York, which is expected to be equipped with ASML\u0026#39;s High NA EUV lithography equipment. IBM is jointly developing processes and equipment for High NA EUV with Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions, and has already demonstrated working devices. IBM has also announced plans to establish Anderon, which it calls the world\u0026#39;s first quantum-dedicated foundry, as an independent business company.\u003c/p\u003e","blueskyPost":"IBM's 0.7nm chip packs 100 billion transistors on a fingernail-sized die using a 3D stacked transistor design called nanostack. The company says it extends Moore's Law by at least 10 years and could reach production within five years.","twitterPost":"IBM says its nanostack 3D transistor architecture can deliver 50% more performance or 70% less power vs its 2nm node. SRAM bit cells shrink 40% in height. No production partners named yet.","threadsPost":null,"newsletterBlurb":"IBM announced a 0.7nm node chip technology using a 3D transistor stacking architecture called nanostack, integrating 100 billion transistors on a fingernail-sized chip. The company claims it extends Moore's Law by at least 10 years and could reach production within five years, though no manufacturing partners have been disclosed.","attributionJson":"[{\"source\":\"ASCII.jp\",\"url\":\"https://ascii.jp/elem/000/004/413/4413774/?rss\",\"title\":\"Beyond the Limits of Miniaturization: IBM's Stacked Chip Extends Moore's Law by 10 Years\"},{\"source\":\"GIGAZINE\",\"url\":\"https://gigazine.net/news/20260626-ibm-0-7-nm-node-nanostack/\",\"title\":\"IBM announces world's first 0.7nm node chip technology, nearly doubling transistor density with 3D 'nanostack' structure\"}]","lintFlagsJson":null,"lintHits":0,"costUsd":0,"inputTokens":9772,"outputTokens":1224,"status":"published","repairAttempts":0,"nextRepairAt":null,"factsAttemptedAt":1782520349,"createdAt":"2026-06-27T00:26:21.000Z","publishedAt":"2026-06-27T00:30:24.000Z","updatedAt":"2026-06-27T00:30:24.000Z"},"cluster":{"id":"c_dd6884db5260706dc210c384","canonicalTitle":"微細化の限界を超え、IBMがムーアの法則を10年伸ばす積層チップ","representativeArticleId":"a_4662819d781d401966e06b97","sourceCount":2,"writtenSourceCount":2,"writeAttempts":0,"isSolo":false,"entitiesJson":"{\"anime_titles\":[],\"manga_titles\":[],\"work_titles\":[],\"studios\":[],\"people\":[],\"type\":\"news\",\"domain\":\"other\",\"is_roundup\":false}","contentType":"news","status":"published","firstSeenAt":"2026-06-25T21:55:56.000Z","lastSeenAt":"2026-06-26T01:57:00.000Z","updatedAt":"2026-06-27T00:30:24.000Z"},"attribution":[{"source":"ASCII.jp","url":"https://ascii.jp/elem/000/004/413/4413774/?rss","title":"微細化の限界を超え、IBMがムーアの法則を10年伸ばす積層チップ"},{"source":"GIGAZINE","url":"https://gigazine.net/news/20260626-ibm-0-7-nm-node-nanostack/","title":"IBMが世界初とする0.7nmノードのチップ技術を発表、3D構造「nanostack」でトランジスタ密度をほぼ2倍に"}],"entities":{"anime_titles":[],"manga_titles":[],"work_titles":[],"studios":[],"people":[],"type":"news","domain":"other","is_roundup":false},"keyFacts":["IBM announced on June 25, 2026, the world's first 0.7nm (7 angstrom) node chip technology using a 3D transistor architecture called nanostack.","The chip integrates approximately 100 billion transistors on a fingernail-sized area, nearly doubling transistor density compared to IBM's 2nm node from 2021.","IBM claims the technology delivers up to 50% higher performance or 70% higher energy efficiency versus the 2nm node.","At the VLSI 2026 symposium, IBM showed that SRAM bit cells using nanostack can reduce height by 40%, enabling more SRAM on the same chip area for AI data bandwidth.","IBM validated the design through ultra-thin dielectric bonding in CMOS integration and demonstrated working CMOS inverters."]}